Devices such as computers and mobile phones may include a processor and a plurality of reusable circuit units, commonly referred to as logic blocks. These logic blocks may be produced by different third-party entities to perform certain functionalities for the devices. For example, computers may include a processor such as a central processing unit (CPU) and logic blocks such as graphics processing units (GPUs), hard disks (HDs), and I/O peripherals. The processor may be programmed with software instructions to execute certain functions including interactions with the logic blocks. Often times, a logic block may need immediate attention from the processor to deal with special situations. For example, a logic block may have a hardware error that may need to be resolved by the processor immediately, or the logic block may have special situations (such as receiving data) that may need to notice the processor immediately. In such events, the logic block may generate one or more interrupts to the processor to inform about the immediate needs by the logic block.
FIG. 1 illustrates a device that includes a processors and logic blocks working collaboratively through an interrupt scheme. Referring to FIG. 1, a device 10 may include a processor 12 and a plurality of logic blocks 16.1-16.4. The processor 12 may be programmed to execute scheduled operations according to an instruction stream. Each of logic blocks 16.1-16.4 may, at the instruction of the processor 12 or controllers embedded in these logic blocks, perform their respective function. The processor 12 may communicate with logic blocks 16.1-16.4 through a bus system 15 so that processor 12 may send execution instructions to and read status information from logic blocks 16.1-16.4. Processor 12 may include an interrupt pin 14 that, if triggered, may cause processor 12 to temporally suspend the execution of the on-going instruction stream and initiate special codes to service the interrupt. Thus, upon receiving an interrupt, processor 12 may first finish the currently executing instruction, save all the data that is necessary for resuming the currently executing instruction stream, and suspend the current instruction stream. Further, the processor may, based on the type of interrupt, start to execute a special program (such as a driver software) that services the interrupt from these logic blocks.
Each of logic blocks 16.1-16.4 may include a respective interrupt controller 19.1-19.4 that may generate an interrupt if an interrupt event occurs. Further, each of logic blocks 16.1-16.4 may include a respective pin 17.1-17.4 for outputting the generated interrupt signal. Pins 17.1-17.4 may be respectively connected to pin 14 of the processor so that processor 12 may receive the generated interrupts from logic blocks 16.1-16.4. Further, logic blocks 16.1-16.4 may each include a read and clear register (RC) 18.1-18.4 that may store status information of interrupts so that processor 12 may read the status information from RC 18.1-18.4 through bus system 15. Thus, in response to the occurrence of interrupting events, logic blocks 16.1-16.4 may save interrupt status information in their respective RC 18-18.4. Thus, in response to the receipt of an interrupt from a logic block at pin 14, processor 12 may suspend the on-going instruction stream and start a special program to service the interrupt. The special program may include read interrupt status information from the corresponding RC and after servicing the interrupt, clear the corresponding RC through the bus system 15.
With the ever increasing sophistication of electronic devices, a device may include numerous logic blocks that generate a large amount of interrupts that require immediate attention from processor 12. Thus, any delays during handling interrupts may degrade the performance of the device. For example, since RC 18.1-18.4 reside on logic blocks, processor 12 needs to use the slower I/O read and write instructions to access RC 18.1-18.4. Since RC 18.1-18.4 reside on logic blocks, they may not be mapped as cacheable memory to the processor. Thus, the read/clear operations of RC 18.1-18.4 may be slow and degrade device performance. Thus, it may not be desirable for processor 12 to retrieve interrupt status information from RC 18.1-18.4.